A New Enhanced delayed lock loop Design using stand by switch for reduced sub-threshold leakage current

Dual threshold voltages domino design methodology utilizes low threshold voltages for all transistors that can switch during the evaluate mode and utilizes high threshold voltages for all transistors that can switch during the pre charge modes. We employed standby switch can strongly turn off all of the high threshold voltage transistors which enhances the effectiveness of a dual threshold voltage CMOS technology to reduce the sub threshold leakage current. An ultra wide-range delay-locked loop (DLL) has been fabricated in 70nm CMOS technology. The modified standby reduction delay unit(SRDU) can easily generate a large propagation delay to reduce the difficulties to build up the highspeed digital counter in the cycle-controlled delay unit (CCDU) for a very low-frequency operation. The proposed DLL circuit can operate from 500 KHz to 1 GHz, and the power consumption is verified using Micro wind & DSCH simulation results under the process of 70nm technology thus the efficiency of the circuit is verified and compared with the DLL made up of 65nm technology.